Host-I/F Registers; Host-I/F Registers Overview - NEC µPD72257 Preliminary User's Manual

Host CPU Interface

5.7 Host-I/F Registers

5.7.1 Host-I/F registers overview

Table 5-6
The Host CPU I/F is controlled and operated by means of the following registers:
System Controller registers overview
Register function
Host-I/F status register
Host-I/F version register
Interrupt status register
Interrupt enable register
Interrupt input register
Host-I/F DMA control register
ADBus base address 0 register
ADBus base address 1 register
ADBus base address 2 register
ADBus base address 3 register
32-bit access to 8-bit/16-bit registers
All registers can be accessed with 32-bit access.
However writing to bits not specified for registers with less than 32 bit width is
ignored and reading of these bits return an undefined value:
• 32-bit access to 8-bit registers
- reading of bit[31:8]: undefined values
- writing to bit[31:8]: ignored
• 32-bit access to 16-bit registers
- reading of bit[31:16]: undefined values
- writing to bit[31:16]: ignored
Preliminary User's Manual S19203EE1V3UM00
Name Address
0000 0000
HOSTSTATUS
HOSTVERSION 0000 000C
0000 0010
HOSTINTSTAT
HOSTINTENAB 0000 0014
0000 0018
HOSTINTFLAG
HOSTCONTROL 0000 001C
HOSTADBASE0 0000 0020
HOSTADBASE1 0000 0024
HOSTADBASE2 0000 0028
HOSTADBASE3 0000 002C
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