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External Memory Interface Controller
9.6.2.3
Access
Address
Initial Value
31
30
29
28
0
0
0
0
R
R
R
R
15
14
13
12
Caution
Bit
Bit name
19 to 16
INITREF[3:0]
15 to 0
TINIT[15:0]
MEMSTMG1R - SDRAM timing register 1
This register defines various timing parameters of the SDRAM initialization phase
after system start-up.
All values are given in system clock periods 1/f
This register can be read/written in 32-bit units.
<MemC_Base> + 08
H
0007 0008
. This register is initialized by any reset.
H
27
26
25
24
0
0
0
0
R
R
R
R
11
10
9
8
TINIT[15:0]
Writing to the read-only bits is ignored, reading returns undefined values.
The default value "0" of bits 21 and 20 must not be changed.
Function
INITREF[3:0] defines the number of auto-refreshes during initialization of the SDRAM.
0
1 refresh
H
1
2 refreshes
H
...
...
7
8 refreshes (default)
H
...
...
F
16 refreshes
H
TINIT[15:0] defines the time to hold SDRAM inputs stable after power-up, before issuing
any commands.
0000
0 clock
H
0001
1 clocks
H
...
...
0008
8 clocks (default)
H
...
...
FFFF
65535 clocks
H
Preliminary User's Manual S19203EE1V3UM00
HCLK
23
22
21
0
0
0
R
R
R/W
R/W
7
6
5
R/W
Chapter 9
.
20
19
18
17
0
INITREF[3:0]
R/W
4
3
2
1
16
0
319
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