NEC µPD72257 Preliminary User's Manual page 146

Chapter 5
5.7.2.3
Interrupt n
Access
Address
Initial Value
31 30 29 28
INTST INTST INTST INTST
AT31 AT30 AT29 AT28
R R R R
15 14 13 12
INTST INTST INTST INTST
AT15 AT14 AT13 AT12
R R R R
Bit Bit name
31 to 3 INTSTAT[31:3]
2 INTSTAT2
1 INTSTAT1
0 INTSTAT0
146
HOSTINTSTAT - Interrupt status register
This register shows the status of the interrupt n.
The available interrupt of this device are defined in the first section of this chapter
under the key word "Interrupts".
This register can be read in 32-bit units.
0000 0010
H
0000 0000 . This register is initialized by any reset.
H
27 26 25 24
INTST INTST INTST INTST
AT27 AT26 AT25 AT24
R R R R
11 10 9 8
INTST INTST INTST INTST
AT11 AT10 AT9 AT8
R R R R
Function
Status of interrupt n
0 interrupt n not pending
1 interrupt n pending
AHB_ERR interrupt status
0 AHB_ERR interrupt not pending
1 AHB_ERR interrupt pending
AHB_OVERRUN interrupt status
0 AHB_OVERRUN interrupt not pending
1 AHB_OVERRUN interrupt pending
AHB_UNDERRUN interrupt status
0 AHB_UNDERRUN interrupt not pending
1 AHB_UNDERRUN interrupt pending
Preliminary User's Manual S19203EE1V3UM00
23 22 21 20
INTST INTST INTST INTST
AT23 AT22 AT21 AT20
R R R R
7 6 5 4
INTST INTST INTST INTST
AT7 AT6 AT5 AT4
R R R R
Host CPU Interface
19 18 17 16
INTST INTST INTST INTST
AT19 AT18 AT17 AT16
R R R R
3 2 1 0
INTST INTST INTST INTST
AT3 AT2 AT1 AT0
R R R R