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Host CPU Interface
(4)
Figure 5-11
5.4 Address Alignment
Caution
ADBus principle read timing with wait
HADA[20:0]
HADCS
HADRD
HADD[15:0]
HADWAIT
1
ADBus principle read timing with wait
1.
HADWAIT falling edge because of HADCS falling edge
2.
HADWAIT rising edge after HADRD falling edge
3.
HADWAIT falling edge after HADRD rising edge
4.
delayed HADWAIT rising edge after HADRD falling edge and wait
time
5.
HADWAIT rising edge because of HADCS rising edge
The LBus-I/F as well as the ADBus-I/F allow to transfer data in byte, half-word
and word size.
•
the data size of LBus-I/F transfers is specified by the L[1:0]
parameters of the eeShort, eeLong commands
•
the data size of ADBus-I/F transfers is specified by the ADBus
HADBEN[1:0] (byte, half-word) and the word combining function
(word)
Depending on the size of the data transferred via the Host-I/F addresses the
internal address iADDR[27:0] is forcibly aligned to the correct address:
•
low byte transfer: low byte alignment iADD0 = 0
•
high byte transfer: high byte alignment iADD0 = 1
•
half-word transfer: 16-bit alignment iADD0 = 0
•
word transfer: 32-bit alignment iADD[1:0] = 00
Take care for specifying addresses for data transfers, which are aligned to the
size of the data. Otherwise the data access will be carried out on others
addresses due to forced address alignment.
Preliminary User's Manual S19203EE1V3UM00
Address1
Address2
Read Data
2
5
1
3
4
Chapter 5
Read Data
3
5
B
139
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