Timing Signals; Display Data Clock Signal - NEC µPD72257 Preliminary User's Manual

Video Output
Table 7-4

7.3 Timing Signals

7.3.1 Display data clock signal

Display data output formats
Signal
RGB(666)
LCDBPP[2:0] = 101
VOnB5 B5
VOnB4 B4
VOnB3 B3
VOnB2 B2
VOnB1 B1
VOnB0 B0
VOnG5 G5
VOnG4 G4
VOnG3 G3
VOnG2 G2
VOnG1 G1
VOnG0 G0
VOnR5 R5
VOnR4 R4
VOnR3 R3
VOnR2 R2
VOnR1 R1
VOnR0 R0
The data output clock, i.e. the pixel clock, VOnCLK is generated in the System
Controller's clock generator.
The edge of VOnCLK used by the Video Output to output the pixel data can be
selected:
• VOnLCDTIMING2.IPC = 0: data out with rising VOnCLK edge, data
stable at falling edge
• VOnLCDTIMING2.IPC = 1: data out with falling VOnCLK edge, data
stable at rising edge
Preliminary User's Manual S19203EE1V3UM00
True colour modes
RGB(565)
LCDBPP[2:0] = 110
B
B4
B3
B2
B1
B0
undefined
G5
G4
G3
G2
G1
G0
R4
R3
R2
R1
R0
undefined
Chapter 7
CLUT mode
iRGB(1555)
LCDBPP[2:0] = 011
B B
B4
B3
B2
B1
B0
I
G4
G3
G2
G1
G0
I
R4
R3
R2
R1
R0
I
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