NEC µPD72257 Preliminary User's Manual page 306

Chapter 9
9.3.1.4
Figure 9-9
306
Data bus turnaround timing
Below diagram illustrates the timing for consecutive accesses, whereas the data
source, i.e. the device driving the data bus MD[31:0], changes.
This is of concern in case of consecutive
• read and write cycles: "read - write" and "write - read"
• read cycles from different MCSn areas: "read MCSn - read MCSm"
The data bus turnaround time parameter MEMSMTMGRk.TBTA defines the
number of system clocks after completion of an access cycle the interface is kept
in idle state before starting the next access.
HCLK
(internal)
MA[24:0]
MCSn
MSBEN
MSOE
MSWR
MD[31:0]
Data bus turnaround timing
In the diagram above following timing parameter settings are used:
• MEMSMTMGRk.TBTA = 1: 1 clock idle time between two accesses
Preliminary User's Manual S19203EE1V3UM00
External Memory Interface Controller
TBTA TBTA
A0 A1
D0 D1
write read
A2
D2
write