NEC µPD72257 Preliminary User's Manual page 108

Chapter 4
4.7.3.4
Access
Address
Initial Value
31 30 29 28
0 0 0 0
R R R R
15 14 13 12
0 0 0 0
R R R R
Caution
Bit Bit name
11 BOOTMODE11 Level of MODE11 pin: the level of MODE11 must be set to 0, thus BOOTMODE11 = 0.
10 BOOTMODE10
9 BOOTMODE9
8 BOOTMODE8
7 BOOTMODE7
6 BOOTMODE6
BOOTMODE
5 to 4
[5:4]
BOOTMODE
3 to 0
[3:0]
108
SYSBOOTMODE - Boot mode register
This register stores the levels of the pins MODE[11:0] upon release of the external
reset RESET.
This register can be read in 32-bit units.
<SysC_Base> + 0C
H
0000 0MMM with MMM = level of MODE[11:0] pins at reset release
H
27 26 25 24
0 0 0 0
R R R R
11 10 9 8
BOOT BOOT BOOT BOOT
MOD MOD MOD MOD
E11 E10 E9 E8
R R R R
Writing to the read-only bits is ignored, reading returns undefined values.
The default value "0" of bit 13 must not be changed.
Function
Level of MODE10 pin: this pin and bit can be used for application purposes by the
application software.
Level of MODE9 pin: enable internal SRAM
0 internal SRAM disabled
1 internal SRAM enabled
Level of MODE8 pin: selects the graphic controller type
0 Ravin-L
1 Ravin-M
Level of MODE7 pin: enable external SDRAM
0 external SDRAM disabled
1 external SDRAM enabled
Level of MODE6 pin: the level of MODE6 must be set to 0, thus BOOTMODE6 = 0.
Level of MODE[5:4] pins: PLL and clock divider settings
Refer to the description of "SYSPLLCTRL - PLLcontrol register" and "SYSCLKCTRL -
Clock control register".
Level of MODE[3:0] pins: pin multiplex settings
Refer to the chapter "Pin Functions".
Preliminary User's Manual S19203EE1V3UM00
23 22 21 20
0 0 0 0
R R R R
7 6 5 4
BOOT BOOT BOOT BOOT
MOD MOD MOD MOD
E7 E6 E5 E4
R R R R
System Controller
19 18 17 16
0 0 0 0
R R R R
3 2 1 0
BOOT BOOT BOOT BOOT
MOD MOD MOD MOD
E3 E2 E1 E0
R R R R