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Chapter 4
Table 4-5
NDIV[6:0]
n = NDIV + 1
0000000
B
to
invalid
1011011
B
1011100
93
B
1011101
94
B
1011110
95
B
1011111
96
B
1100000
97
B
1100001
98
B
1100010
99
B
1100011
100
B
1100100
B
to
invalid
1111111
B
Table 4-6
Frequency
ADJ[2:0]
dither range
000
ca. 0.5%
B
001
ca. 1.0 %
B
010
ca. 2.0 %
B
011
ca. 3.0 %
B
100
ca. 4.0 %
B
101
ca. 5.0 %
B
110
to 111
invalid
B
B
Table 4-7
MODE[5:4]
SYSPLLCTRL reset value
00
B
(NDIV=99, MDIV=9, PDIV=0, PC=0)
01
B
(NDIV=95, MDIV=11, PDIV=0, PC=0)
10
(NDIV=99, MDIV=9, PDIV=0, PC=1,
B
102
PLL output clock configuration
MDIV[6:0] m = MDIV + 1
0000000
B
0000001
B
0000010
B
0000011
B
0000100
B
0000101
B
...
1111101
B
1111110
B
1111111
B
If frequency dithering is enabled (SYSPLLCTRL.PC = 1), following values must be
defined additionally:
PLL output clock dither parameters configuration
MDL[1:0]
00
B
01
B
10
B
11
B
The default (reset) value of SYSPLLCTRL is determined by the MODE[5:4] pin level
at de-assertion of RESET. Thus one out of 4 default reset PLL configurations can
be chosen after reset according to the table below.
Default PLL modes by MODE[5:4] settings
0000 6309
H
0000 5F0B
H
B510 6309
H
ADJ=5, MDL=3, S=2)
Preliminary User's Manual S19203EE1V3UM00
PDIV[1:0]
00
invalid
B
01
2
B
10
3
B
11
4
B
5
6
...
126
127
128
Modulation
frequency range
15 KHz to 25 KHz
25 KHz to 35 KHz
34 KHz to 46 KHz
45 KHz to 65 KHz
Assumed f
CLKIN
16 MHz
20 MHz
16 MHz
System Controller
f
PLLCLKOUT
p = PDIV
[MHz}
0
100 - 160
1
50 - 100
2
25 - 50
invalid
invalid
f
= f
VCOIN
CLKIN
S[1:0]
range [MHz]
00
1.00 ≤ f
B
VCOIN
01
1.20 ≤ f
B
VCOIN
10
1.45 ≤ f
B
VCOIN
11
1.70 ≤ f
B
VCOIN
Resulting f
PLLCKOUT
160 MHz
160 MHz
160 MHz
(dithering on:
modulation frequency 45 - 65 KHz,
dither range ca. 5%)
/ m
< 1.20
< 1.45
< 1.70
< 2.00
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