NEC µPD72257 Preliminary User's Manual page 184

Graphics controllers
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Chapter 6
6.10.2.12
Access
Address
Initial Value
31
30
29
28
0
0
0
0
R
R
R
R
15
14
13
12
0
0
R
R
Bit
Bit name
13 to 8
FFUSEDW[5:0] Number of words in FIFO
7
VIIDLE
6
FIELD
5
VSYNC
4
HSYNC
1
START2PEND
0
START1PEND
184
VInSTATUS - Video Input status register
This register summarizes all status information for the Video Input.
This register can be read in 32-bit units.
<VIn_Base> + 20
H
0000 0000 0000 0000 00XX XXXX XXXX 00XX
reset.
27
26
25
24
0
0
0
0
R
R
R
R
11
10
9
8
FFUSEDW[5:0]
R
Function
Operation status of Video Input
0 capture operation active
1 idle
Current status of the internal field signal
0 first field
1 second field
Current status of the internal VSYNC signal
0 not active
1 active
Current status of the internal HSYNC signal
0 not active
1 active
New address in VInSTARTADDR2 for second field pending
0 new VInSTARTADDR2 effective
1 new VInSTARTADDR2 not yet effective
New address in VInSTARTADDR1 for first field pending
0 new VInSTARTADDR1 effective
1 new VInSTARTADDR1 not yet effective
Preliminary User's Manual S19203EE1V3UM00
Video Input (Ravin-M only)
. This register is initialized by any
B
23
22
21
20
0
0
0
0
R
R
R
R
7
6
5
4
VI
V
H
FIELD
IDLE
SYNC
SYNC
R
R
R
R
19
18
17
16
0
0
0
0
R
R
R
R
3
2
1
0
STAR
STAR
0
0
T2
T1
PEND
PEND
R
R
R
R

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