Sdram Interface - NEC µPD72257 Preliminary User's Manual

Chapter 9
AHB
Figure 9-1

9.2 SDRAM Interface

SDRAM chip selects
SDRAM feedback
clock
294
Address
and data
FIFO
HCLK
Memory Controller block diagram
SDRAM can be assigned to the chip select area MCS0. Thus the memory type
selection of MCS1 must not be set to SDRAM
(MEMSMSKR1.MEMTYPE[2:0] ≠ 000
In order to compensate signal delays of the memory bus signals on the off-chip
PCB, the data MD[31:0] signals are sampled with the SDRAM feed-back clock
MDFBCLK instead of MDCLK for data read accesses. Sampling of the read data
signals MD[31:0] with MDFBCLK applies only if data is read from the external
SDRAM, i.e.
• SDRAM is enabled by SDRAMEN = 1
• SRAM chip select is not active, i.e. MCS1 = 1
In case of SRAM or flash the read data is registered with MDCLK.
The feed-back clock MDFBCLK have to be connected externally with MDCLK.
Also the read pipe have to be set accordingly. This is ensured by the default value
010 of bits 8 to 6 in the SDRAM control register MEMSCTLR.
B
Preliminary User's Manual S19203EE1V3UM00
External Memory Interface Controller
Address decoder
SDR-SDRAM controller
Static memory controller
Registers
SDRAMEN
).
B
MA[24:0]
MD[31:0]
MCS0
MCS1
MDBA[1:0]
MDDQM[3:0]
MDRAS
MDCAS
MDWE
MDCKE
MDCLK
MDFBCLK
MDA10PC
MSOE
MSWR
MSBEN[3:0]