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Chapter 9
9.6.2.7
Access
Address
Initial Value
31
30
29
28
0
0
0
0
R
R
R
R
15
14
13
12
0
0
0
0
R
R
R
R
Bit
Bit name
10 to 8
REGSEL[2:0]
7 to 5
MEMTYPE[2:0]
4 to 0
MEMSIZE[4:0]
324
MEMSMSKRn - Chip select address mask registers
These registers define the memory type and its size for each chip select. In case
of static memory types, a certain set of timing registers is selected.
A separate chip select address mask register is available for each chip select n.
These registers can be read/written in 32-bit units.
•
MEMSMSKR0: <MemC_Base> + 54
•
MEMSMSKR1: <MemC_Base> + 58
•
MEMSMSKR0: 0000 0209
•
MEMSMSKR1: 0000 024B
These registers are initialized by any reset.
27
26
25
24
0
0
0
0
R
R
R
R
11
10
9
8
0
REGSEL[2:0]
R
R/W
Writing to the read-only bits is ignored, reading returns undefined values.
Function
REGSEL[2:0] determines which timing parameter register use MEMSMTMGk of memory
connect to chip select n is to be used. This is only of concern for static memory types
SRAM and flash memory.
000
use MEMSMTMG0
B
001
use MEMSMTMG1
B
010
use MEMSMTMG2 (default)
B
MEMTYPE[2:0] defines the type of memory connected to corresponding chip select n.
000
SDRAM (MCS0 default)
B
001
SRAM
B
010
flash (MCS1 default)
B
all other prohibited
Caution:
SDRAM must not be assigned to MCS1, thus MEMSMSKR1.MEMTYPE[2:0] must
not be set to 000
.
B
MEMSIZE[4:0] defines the size of memory connected to corresponding chip select n.
The memory size is calculated by 2
Preliminary User's Manual S19203EE1V3UM00
External Memory Interface Controller
H
H
H
H
23
22
21
20
0
0
0
0
R
R
R
R
7
6
5
4
MEMTYPE[2:0]
R/W
(mem_size[4:0]-1)
• 64 KB.
19
18
17
16
0
0
0
0
R
R
R
R
3
2
1
0
MEMSIZE[4:0]
R/W
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