NEC µPD72257 Preliminary User's Manual page 183

Video Input (Ravin-M only)
6.10.2.11
Access
Address
Initial Value
31 30 29 28
0 0 0 0
R R R R
15 14 13 12
0 0 0 0
R R R R
Bit Bit name
25 to 16 34SCN[9:0]
9 to 0 14SCN[9:0]
VInSYNCDECODE - CSYNC separator control register
This register controls the composite synchronization signal CSYNC separator.
Generation of the strobe signals at 1/4 and 3/4 of a scanline can be defined in
multiples of 64 pixels.
This register can be read/written in 32-bit units.
<VIn_Base> + 2C
H
0000 0000 . This register is initialized by any reset.
H
27 26 25 24
0 0 34SCN[9:6]
R R
11 10 9 8
0 0 14SCN[9:6]
R R
Writing to the read-only bits is ignored, reading returns undefined values.
Function
3/4 scanline
Lower bits 34SCN[5:0] must be fixed to 0 due to 64-pixel alignment
1/4 scanline
Lower bits 14SCN[5:0] must be fixed to 0 due to 64-pixel alignment
Preliminary User's Manual S19203EE1V3UM00
23 22 21
R/W
7 6 5
R/W
Chapter 6
20 19 18 17
34SCN[5:0]
R/W
4 3 2 1
14SCN[5:0]
R/W
16
0
183