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External Memory Interface Controller
9.2.1 SDRAM Initialization
The Memory Controller follows the JEDEC-recommended SDR-SDRAM power-
on initialization sequence as follows:
1.
Upon power appliance and clock start, NOP condition is maintained
for a minimum of MEMSTMG1R.TINIT clock cycles.
2.
Precharge commands for all banks are issued.
3.
Auto-refresh commands are issued, depending on the value
MEMSTMG1R.INITREF.
4.
The mode registers of the SDRAM devices are written.
The Memory Controller performs a power-on sequence of the SDRAM under
these circumstances:
•
immediately after reset
•
when initialization is commenced by setting MEMSCTRL.INIT = 1
If the initialization sequence is completed, MEMSCTRL.INIT is
automatically reset to 0.
Preliminary User's Manual S19203EE1V3UM00
Chapter 9
295
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