NEC µPD72257 Preliminary User's Manual page 298

Chapter 9
Table 9-2
298
If the SDRAM needs to be refreshed while a burst is active, the Memory Controller
will issue the refresh command after the ongoing burst completes. Thus the
maximum time to complete a worst-case burst has to be taken into account.
row_refresh_period = SDRAM_refresh_period / num_of_rows >
max_burst_clocks / f
That leads to the condition for the minimum system clock frequency, necessary
to keep the SDRAM_refresh_period within the given limit:
f ≥ (num_of_rows • max_burst_clocks) / SDRAM_refresh_period
HCLK
with - f is the system clock frequency
HCLK
- num_of_rows the number of rows to refresh
- max_burst_clocks: the maximum number of system clocks for a burst
It is reasonable to assume 50 cycles for this worst-case burst, with 32 cycles for
the data and the remaining 17 cycles for various latencies for the worst case.
With the typical values of max_burst_clocks = 50 and
SDRAM_refresh_period = 64 ms following equation calculates the minimum
frequency in MHz:
f [MHz] ≥ num_of_rows / 1280
HCLK
Following table gives some values for the minimum system clock frequency
f for different number of rows to refresh for a maximum burst length of
HCLK
max_burst_clocks = 50 f
64 ms. f is rounded up.
HCLK
The possible MEMSREFR.TREF settings are also given, based on the rounded up
f .
HCLK
Note that MEMSREFR.TREF must be set to at least to the number of clocks for a
maximum burst, i.e. 50.
Minimum frequency requirement
Number of Rows
64 K
32 K
16 K
8 K
4 K
2 K
The refresh logic is inactive when the Memory Controller forces the SDRAM into
self-refresh or power-down mode.
Below figure illustrates the command sequence issued by the SDRAM controller
when performing an auto-refresh.
MEMSTMG0R.TRCAR[3:0] defines the minimum time to wait after auto-refresh
before a next auto-refresh or any other command is performed.
Preliminary User's Manual S19203EE1V3UM00
External Memory Interface Controller
HCLK
periods and a typical SDRAM_refresh_period of
HCLK
MEMSREFR.TREF
51
51
51
55
63
63
Minimum f
HCLK
52 MHz
26 MHz
13 MHz
7 MHz
4 MHz
2 MHz