NEC µPD72257 Preliminary User's Manual page 106

Chapter 4
IRAMCLKEN default
(Ravin-L only)
VOxDIV/BUSDIV
default
Table 4-10
Table 4-11
106
The IRAMCLKEN default value is subject to the boot mode function and takes on
the level of MODE9 at RESET release:
• MODE9 = 0 IRAMCLKEN = 0: internal SRAM disabled after RESET
• MODE9 = 1 IRAMCLKEN = 1: internal SRAM enabled after RESET
The VOxDIV[5:0] and BUSDIV[1:0] values are subject to the boot mode function
and take on the level of MODE4 at RESET release.
In conjunction with the default values of the PLL control settings, which depend
on MODE4, two different HCLK, VO0CLK/VO1CLK start-up values can be chosen
for Ravin-L and Ravin-M by setting of the external pins, refer to Table 4-10
repspectively Table 4-11 .
The frequencies of VOxCLK and HCLK are calculated as follows:
• f = f
VOxCLK PLLCLKOUT
• f = f
HCLK PLLCLKOUT
The tables below summarize the default clock settings for Ravin-L respectively
Ravin-M under the assumption that SYSPLLCTRL holds any of the default
settings and has not been modified, i.e. f
Ravin-L default clock settings
SYSCLKCTRL[23:0]
MODE4
reset value
3F 0317
0
(BUSDIV=3, VO0DIV=23,
VO1DIV=63)
3F 032F
1
(BUSDIV=3, VO0DIV=47,
VO1DIV=63)
Ravin-M default clock settings
SYSCLKCTRL[23:0]
MODE4
reset value
17 0105
0
(BUSDIV=1, VO0DIV=5,
VO1DIV=23)
17 0104
1
(BUSDIV=1, VO0DIV=4,
VO1DIV=23)
Preliminary User's Manual S19203EE1V3UM00
/ (VOxDIV + 1)
/ (BUSDIV + 1)
PLLCLKOUT
Resulting
f
HCLK
H
40 MHz
H
40 MHz
Resulting
f
HCLK
H
80 MHz
H
80 MHz
System Controller
= 160 MHz.
Resulting Resulting
f f
VO0CLK VO1CLK
6.6 MHz 2.5 MHz
3.3 MHz 2.5 MHz
Resulting Resulting
f f
VO0CLK VO1CLK
26.6 MHz 6.6 MHz
32 MHz 6.6 MHz