NEC µPD72257 Preliminary User's Manual page 214

Chapter 7
7.7.2.10
Access
Address
Initial Value
31 30 29 28
0 0 0 0
R R R R
15 14 13 12
0 0 0 0
R R R R
Bit Bit name
4 MBERRORMIS
3 VCOMPMIS
2 LNBUMIS
1 FUFMIS
214
VOnLCDMIS - Masked interrupt status register
This register monitors the status of all system interrupts.
The system interrupts are unmasked (enabled) raw interrupts. The raw interrupts
status is shown in the raw interrupt status register VOnLCDRIS.
The interrupt status can be changed from pending to inactive by writing a 1 to the
corresponding bit in the interrupt clear register VOnLCDICR.
This register can be read in 32-bit units.
<VOn_Base> + 024
H
0000 0000 . This register is initialized by any reset.
H
27 26 25 24
0 0 0
R R R
11 10 9
0 0 0
R R R
Function
AHB master error interrupt VOnBEINT status bit
0 VOnBEINT pending
1 VOnBEINT inactive
Vertical compare interrupt VOnVCPINT status bit
0 VOnVCPINT pending
1 VOnVCPINT inactive
LCD next address base update interrupt VOnBAINT status bit
0 VOnBAINT pending
1 VOnBAINT inactive
FIFO underflow interrupt VOnFUFINT status bit
0 VOnFUFINT pending
1 VOnFUFINT inactive
Preliminary User's Manual S19203EE1V3UM00
23 22 21
0 0 0 0
R R R R
8 7 6 5
0 0 0 0
R R R R
Video Output
20 19 18 17
0 0 0 0
R R R R
4 3 2 1
MBER VCO
LNBU FUF
ROR MP
MIS MIS
MIS MIS
R R R R
16
0
R
0
0
R