NEC µPD72257 Preliminary User's Manual page 105

System Controller
Bit Bit name
9 to 8 BUSDIV[1:0]
5 to 0 VO0DIV[5:0]
Caution
Reset values
Table 4-8
Table 4-9
SDREN default
Function
Divider for the main system clock HCLK
00 f = f
B HCLK PLLCLKOUT
01 f = f
B HCLK PLLCLKOUT
10 f = f
B HCLK PLLCLKOUT
11 f = f
B HCLK PLLCLKOUT
Divider for Video Output clock VO0CLK
0
f = f
VO0CLK PLLCLKOUT
1
f = f
2
VO0CLK PLLCLKOUT
... ...
f = f
62
VO0CLK PLLCLKOUT
f = f
63
VO0CLK PLLCLKOUT
If SYSCLKCTRL.BUSDIV is changed, a software reset by
SYSRESET.SWRESET = 1 must be issued.
Below tables defines the initial values of the SYSCLKCTRL register for Ravin-L
and Ravin-M.
Ravin-L SYSCLKCTRL reset values
MODE9
(IRAMCLKEN)
0
0
0
0
1
1
1
1
Ravin-M SYSCLKCTRL reset values
MODE7
(SDREN)
0
0
1
1
The SDREN default value is subject to the boot mode function and takes on the
level of MODE7 at RESET release:
• MODE7 = 0 SDREN = 0: SDRAM disabled after RESET
• MODE7 = 1 SDREN = 1: SDRAM enabled after RESET
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MODE7 MODE4
(SDREN) (dividers)
0
0
1
1
0
0
1
1
MODE4
(dividers)
0
1
0
1
Chapter 4
Reset value
003F 0317
0
003F 032F
1
803F 0317
0
803F 032F
1
403F 0317
0
403F 032F
1
C03F 0317
0
C03F 032F
1
Reset value
0017 0105
H
0017 0104
H
8017 0105
H
8017 0104
H
H
H
H
H
H
H
H
H
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