Pll Configuration - NEC µPD72257 Preliminary User's Manual

System Controller

4.2.1 PLL configuration

Figure 4-3
Boot mode
The PLL is configured by a set of parameters, derived from the SYSPLLCTRL
register.
The frequency of PLLCLKOUT is calculated as follows:
f = f x (n/m) x 1/2
PLLCLKOUT CLKIN
The values n, m, p are derived from SYSPLLCTRL register bits:
• n = SYSPLLCTRL.NDIV[6:0] + 1
• m = SYSPLLCTRL.MDIV[6:0] + 1
• p = SYSPLLCTRL.PDIV[1:0]
If frequency dithering is enabled (SYSPLLCTRL.PC = 1), additional parameters
must be set in SYSPLLCTRL:
• SYSPLLCTRL.S[1:0] must be set in accordance with the frequency
f = f /m
VCOIN CLKIN
• SYSPLLCTRL.MDL[1:0] determines the modulation frequency
range, i.e. the time the output frequency is from its maximum to its
minimum and vice versa
• SYSPLLCTRL.ADJ[2:0] determines the frequency dither range, i.e.
the maximum and minimum frequency
Concerning the allowed settings of the PLL parameters refer to the description of
the SYSPLLCTRL register.
SYSPLLCTRL.
VCOIN
1/m
CLKIN
SYSPLLCTRL.
MDIV[6:0]
PLL configuration
New PLL parameters set up in SYSPLLCTRL are becoming effective only after a
reset has been applied. While the external RESET takes on one out of the four
predefined parameter sets via the boot mode function, a PLL reset by setting
SYSRESET.PLLRESET = 1 must be applied when SYSPLLCTRL has been
modified by the application software.
For further information concerning the reset function refer to the concerned
chapter "Resets".
The default value of SYSPLLCTRL is subject to the boot mode function and
depends on the MODE[5:4] pin levels at RESET release.
Preliminary User's Manual S19203EE1V3UM00
p
SYSPLLCTRL. SYSPLLCTRL.
PC ADJ[2:0]
SYSPLLCTRL.
S[1:0] MDL[1:0]
PLL & VCO
1/n
SYSPLLCTRL.
NDIV[6:0]
Chapter 4
VCOOUT
p
1/2
PLLCLKOUT
SYSPLLCTRL.
PDIV[1:0]
89