Static Memory Interface; Static Ram Timing - NEC µPD72257 Preliminary User's Manual

Chapter 9

9.3 Static Memory Interface

Static memory chip
selects

9.3.1 Static RAM timing

Note
302
Static memory can be assigned to the chip select areas MCS0 and MCS1.
This section describes the functional details of the Memory Controller as a static
memory controller. Static memory in this context refers to asynchronous SRAMs
and asynchronous nor-flash memories.
The Memory Controller supports static memories of various data widths. It
provides three sets of timing registers MSMTMGRk, with k = 0 to 2, for controlling
the static memory, that allows to set up three different interface timing
specifications. Each chip select area, that is configured for static memory, can be
assigned to one of the timing registers MSMTMGRk.
The chip select area n is configured for static memory by
• MEMSMSKRn.MEMTYPE[2:0] = 001
• MEMSMSKRn.MEMTYPE[2:0] = 010
If static memory is chosen for a chip select, this chip select needs to be associated
with one of three timing registers MEMSMTMGRk (k = 0 to 2) in the chip select
mask register for chip select n:
• MEMSMSKRn.REGSEL[2:0] = k = 0 to 2: timing register MSMTMGRk
assigned to MCSn
In the following the meaning of the timing parameters of the static RAM interface
is explained by using timing diagram and explanation of the parameters.
1. The internal system clock HCLK is included in the diagrams only for
explanatory purposes and does not reflect the correct timing.
2. The byte enable signals MSBEN[3:0] are shown as MSBEN, which
shall depict the concerned MSBEN[3:0] signal of the memory
access.
3. The index k in the register name MEMSMTMGRk means one of the
three timing register sets k = 0 to 2.
Preliminary User's Manual S19203EE1V3UM00
External Memory Interface Controller
: static RAM for MCSn
B
: flash for MCSn
B