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Chapter 5
5.3.4 ADBus-I/F principle timing
(1)
Note
136
Generation of HADWAIT
The wait signal HADWAIT requests the Host CPU to extend the bus timing in case
the ADBus-I/F is still busy transferring the data internally. The Host CPU should
sample the HADWAIT signal and stretch the access cycle upon demand, until the
ADBus-I/F indicates ready status by de-assertion of HADWAIT.
The wait signal HADWAIT behaves as follows:
•
It is asserted with the falling edge of HADCS.
•
It is not released before the falling edge of the HADRD/HADWR
strobe.
•
The rising edge of the HADRD/HADWR strobe sets HADWAIT again
to low level.
•
The rising edge of the HADCS sets HADWAIT back to high level and
completes the access cycle.
Depending on the access type and especially on the occupation of the internal
AHB HADWAIT may be active for some longer time, forcing the Host CPU to
stretch the current access.
In the following some principle timing diagrams are given.
The vertical dash lines in the following diagram serve as a kind of grid and do not
have any relation to the real timing of the signals.
Preliminary User's Manual S19203EE1V3UM00
Host CPU Interface
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