Pll Restart - NEC µPD72257 Preliminary User's Manual

Chapter 4
Reset System
source reset
SYSRESET.
SWRESET
yes
WDRESET
Synchronization

4.3.1 PLL restart

Figure 4-4
Figure 4-5
92
PLL reset
SYSPLLCTRL PLL
reset restart
no no
After any reset has been applied the graphics controller is not operable for a
certain time, which depends on the reset source. During this time the Host CPU
must not access the graphics controller, refer to the section "Host CPU
synchronization" below.
A PLL restart requires some attention concerning the timing of the internally
generated SYSRESET signal.
In order to ensure a stable internal main system clock HCLK prior to release of all
internal modules, the internal SYSRESET remains active for some time after the
PLL restart reset is released. As a consequence all modules will not be in operation
until SYSRESET is deasserted.
The diagrams below outline the initial start timing, initiated by an external
RESET, and restart timing, initiated by SYSRESET.PLLRESET = 1.
RESET
SYSRESET
RESINT
PLL start timing
PLLRESET
SYSRESET
RESINT
PLL restart timing
The start time T
PLLSTART
its frequency of the external resonator at XT1/XT2.
Preliminary User's Manual S19203EE1V3UM00
SYSCLKCTRL
reset
reset of all system functions with
no
continuing clock operation
T
PLLSTART
T
PLLSTART
clear of RESINT
by Host CPU
takes 43000 periods of the oscillator clock CLKIN with
System Controller
Purpose
clear of RESINT
by Host CPU