Video Input Registers Details - NEC µPD72257 Preliminary User's Manual

Chapter 6

6.10.2 Video Input registers details

6.10.2.1
Access
Address
Initial Value
31 30 29 28
15 14 13 12
0
R R R R
Bit Bit name
11 to 8 DITHEN[3:0]
7 RGBSEL
6 YUVSEL
5 SYNCINV
4 to 3 SYNCSEL[1:0]
2 CLKPH
172
VInCONTROL - Video Input control register
This register holds all control bits to operate the Video Input.
This register can be read/written in 32-bit units.
<VIn_Base> + 18
H
0000 0000 . This register is initialized by any reset.
H
27 26 25 24
11 10 9
DITHEN[3:0]
R/W
Writing to the read-only bits is ignored, reading returns undefined values.
Function
Dither control – enables dithering and sets the number of bits to be used for dithering
0000
dithering disabled
B
0001
one bit (0) used for dithering
B
0010
two bits (0 - 1) used for dithering
B
0100
three bits (0 - 2) used for dithering
B
1000
four bits (0 - 3) used for dithering
B
Selects RGB input format
0 input format is RGB(565)
1 input format is RGB(666)
Selects YUV(4:2:2) input format
0 input format is Y1:U:Y2:V
1 input format is U:Y1:V:Y2
Selects polarity of external synchronization signal
0 no inversion of VInSYNC1/VInSYNC2 (active high)
1 inversion of VInSYNC1/VInSYNC2 (active low)
Synchronization signal selection
00
use ITUR-R656 embedded sync mode
B
01
use VInSYNC1 as CSYNC signal
B
10
use VInSYNC1 as HSYNC and VInSYNC2 as VSYNC signal
B
11
reserved
B
Clock phase for data input
Preliminary User's Manual S19203EE1V3UM00
23 22 21
0
R
8 7 6 5
RGB YUVS SYNC
SEL EL INV
R/W R/W R/W
Video Input (Ravin-M only)
20 19 18 17
4 3 2 1
CLK RGB
SYNCSEL[1:0]
PH EN
R/W R/W R/W R/W
16
0
CAP
EN
R/W