NEC µPD72257 Preliminary User's Manual page 334

Chapter 10
Address
0000 1E20H Video Input status
0000 1E24H Active scanline
0000 1E28H Scanline interrupt control
0000 1E2CH VCSYNC separator control
0000 1E30H Scanlines offset
0000 1E34H YUV adjustment control
0000 1E50H Video Input macro version
0000 2000H VO0 Horizontal axis panel control
0000 2004H VO0 Vertical axis panel control
0000 2008H VO0 Clock and signal polarity control
0000 2010H VO0 Framebuffer base address
0000 2018H VO0 Control
0000 201CH VO0 Interrupt mask set/clear
0000 2020H VO0 Raw interrupt status
0000 2024H VO0 Masked interrupt status
0000 2028H VO0 Interrupt clear
0000 202CH VO0 Current address
0000 2200H -
VO0 Colour palette registers
0000 23FCH
0000 3000H SDRAM configuration
0000 3004H SDRAM timing 0
0000 3008H SDRAM timing 1
0000 300CH SDRAM control
0000 3010H SDRAM refresh
0000 3014H Chip select base address 0
0000 3018H Chip select base address 1
0000 3054H Chip select address mask 0
0000 3058H Chip select address mask 1
0000 3074H Chip select alias address 0
0000 3078H Chip select alias address 1
0000 3094H Static memory timing 0
0000 3098H Static memory timing 1
0000 309CH Static memory timing 2
0000 30A4H Static memory control register
0000 4000H VO1 Horizontal axis panel control
0000 4004H VO1 Vertical axis panel control
0000 4008H VO1 Clock and signal polarity control
0000 4010H VO1 Framebuffer base address
0000 4018H VO1 Control
0000 401CH VO1 Interrupt mask set/clear
334
Register name
Preliminary User's Manual S19203EE1V3UM00
Access width in
Shortcut
VI0STATUS –
VI0ACTSCANLINE –
VI0SCANLINEINT –
VI0SYNCDECODE –
VI0STRIDEX –
VI0ADJUSTLEVEL –
VI0REVISION –
VO0LCDTIMING0 –
VO0LCDTIMING1 –
VO0LCDTIMING2 –
VO0LCDUPBASE –
VO0LCDCONTROL –
VO0LCDIMSC –
VO0LCDRIS –
VO0LCDMIS –
VO0LCDICR –
VO0LCDUPCURR –
VO0LCDPALETTE –
MEMSCONR –
MEMSTMG0R –
MEMSTMG1R –
MEMSCTLR –
MEMSREFR –
MEMSCSLR0 –
MEMSCSLR1 –
MEMSMSKR0 –
MEMSMSKR1 –
MEMCSALIAS0 –
MEMCSALIAS1 –
MEMSMTMGR0 –
MEMSMTMGR1 –
MEMSMTMGR2 –
MEMSMCTRL –
VO1LCDTIMING0 –
VO1LCDTIMING1 –
VO1LCDTIMING2 –
VO1LCDUPBASE –
VO1LCDCONTROL –
VO1LCDIMSC –
Register List
bit
8 16 32
– R
– R
– R/W
– R/W
– R/W
– R/W
– R
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R
– R
– R
– R
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W
– R/W