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Chapter 8
8.9.2.3
Access
Address
Index
Initial Value
Bit
Bit name
5
BUSIRQCLR
4
BUSIRQEN
3
DLISTIRQCLR
2
ENUMIRQCLR
260
DRWIRQCTL - Interrupt control register
This register enables interrupts and clears the interrupt status.
This register can be written in 32-bit units.
<DrwE_Base> + C0
H
48
0000 0000
. This register is initialized by any reset.
H
31
30
0
0
W
W
23
22
0
0
W
W
15
14
0
0
W
W
7
6
BUSIRQC
0
0
W
W
Wrting to bits marked with "0" is ignored.
Function
Clear bus error interrupt BUSIRQ
0 no BUSIRQCLR clear
1 clear BUSIRQCLR
After writing "1" this bit returns to "0" automatically.
BUSIRQ interrupt mask enable
0 disable (mask) BUSIRQ
1 enable (unmask) BUSIRQ
Clear display list interrupt DLISTIRQ
0 no BUSIRQCLR clear
1 clear BUSIRQCLR
After writing "1" this bit returns to "0" automatically.
Clear enumeration interrupt ENUMIRQ
0 no ENUMIRQ clear
1 clear ENUMIRQ
After writing "1" this bit returns to "0" automatically.
Preliminary User's Manual S19203EE1V3UM00
29
28
27
0
0
0
W
W
W
21
20
19
0
0
0
W
W
W
13
12
11
0
0
0
W
W
W
5
4
3
BUSIRQE
DLISTIRQ
LR
N
CLR
W
W
W
Drawing Engine
26
25
24
0
0
W
W
W
18
17
16
0
0
W
W
W
10
9
0
0
W
W
W
2
1
ENUMIRQ
DLISTIRQ
ENUMIRQ
CLR
EN
EN
W
W
W
0
0
8
0
0
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