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Chapter 7
VOnCLK
Video data
IPC = 0
Video data
IPC = 1
Figure 7-2
7.3.2 Synchronization signals
Table 7-5
Register
VOnLCDTIMING0.HBP[7:0]
VOnLCDTIMING0.HFP[7:0]
VOnLCDTIMING0.HSW[7:0]
VOnLCDTIMING0.PPL[5:0]
VOnLCDTIMING1.VBP[7:0]
VOnLCDTIMING1.VFP[7:0]
VOnLCDTIMING1.VSW[5:0]
VOnLCDTIMING1.LPP[9:0]
194
VOnCLK timing setting
The Video Output module generates following synchronization signals:
•
VOnVSYNC: vertical (frame) synchronization signal
VOnVSYNC can generate a video data enable signal VOnEN
optionally, controlled by settings in the Video Output control register
in the System Controller:
-
SYSVOCTRL.VOnVSSELn = 0: VOnVSYNC output
-
SYSVOCTRL.VOnVSSELn = 1: VOnEN output
•
VOnHSYNC: horizontal (line) synchronization signal
VOnHSYNC can generate a composite synchronization signal
VOnCSYNC optionally, controlled by settings in the Video Output
control register in the System Controller:
-
SYSVOCTRL.CSYNCSELn = 0: VOnHSYNC output
-
SYSVOCTRL.CSYNCSELn = 1: VOnCSYNC output
The timing of VOnVSYNC and VOnHSYNC (and whereby also of VOnCSYNC)
synchronization signals are programmable via the registers VOnLCDTIMING0 and
VOnLCDTIMING1.
These registers allow also to define the output width and height.
The unit for the various values are pixel clocks for horizontal and lines for vertical
synchronization timing.
Following timings are to be defined:
Synchronization timing registers
Function
Horizontal back porch width
Horizontal front porch width
Horizontal synchronization pulse width
Pixels/line
Vertical back porch width
Vertical front porch width
Vertical synchronization pulse width
Lines/frame
Preliminary User's Manual S19203EE1V3UM00
Video Output
Range
3 to 256 pixels
1 to 256 pixels
3 to 256 pixels
16 to 1024 pixels/line
0 to 255 lines
0 to 255 lines
1 to 64 lines
1 to 1024 lines/field
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