NEC µPD72257 Preliminary User's Manual page 13

Introduction
Ravin-L
HLBD[7:0]
HLBWR
HLBRD
HLBCS
HLBDRQ
Host-I/F
HINT
RAM
160 KB
VO0R[5:0]
VO0G[5:0]
Video
VO0B[5:0]
Output
VO0HSYNC
VO0VSYNC
VO0CLK
VO0EN
Figure 1-2
Busses
APB
APB master
HCLK
SYSRESET
AHB master
HCLK
SYSRESET
AHB slave
AHB slave
SYSRESET
VO0CLK
0
AHB master
Ravin-L block diagram
The internal modules are linked via two bus systems:
• APB
The APB is used to give the external Host CPU access the control
registers of the System Controller, Video Input and Drawing Engine.
The Host-I/F module is the only APB master.
AHB
•
The main purpose of the AHB is to transfer video and image content
data. Since the Video Input and Output modules, the Drawing Engine
as well as the Host CPU deal with video data, these modules can
access the AHB as bus masters. All video and image data is stored
in framebuffers in external memory and - with Ravin-L - in the internal
RAM. Hence the external and internal memory are connected as
slave AHB clients. The control registers of External Memory I/F
Controller are also accessible via its AHB slave I/F.
The AHB is also used to access the Video Output modules control
registers, whcih are equipped with AHB slave interfaces for that
purpose.
Preliminary User's Manual S19203EE1V3UM00
AHB
AHB master
Drawing
HCLK
Engine
SYSRESET
APB slave Slave
HCLK
AHB slave
SYSRESET
HCLK
VO0CLK
System
SYSRESET
Controller
APB slave
Chapter 1
MD[15:0]
MA[24:0]
MCS0
MCS1
MDBA[1:0]
MDDQM[1:0]
MDRAS
MDCAS
MDWE
MDCKE
MDCLK
MDFBCLK
MDA10PC
MSOE
MSWR
MSBEN[1:0]
RESET
XT1
XT2
13