Powerquicc Ii Integrated Processor Core Block Diagram - Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual

G2 Core
System
Register
Unit
+
Integer
Unit
/ +
*
XER
Completion
Unit
Power
Dissipation
Control
JTAG/COP
Interface
Figure 2-1. PowerQUICC II Integrated Processor Core Block Diagram
2-2
Sequential
Fetcher
Instruction
Queue
Dispatch Unit
32-Bit
GPR File
Load/Store
Unit
GP Rename
Registers
D MMU
SRs
DTLB
Time Base
Counter/
Decrementer
Tags
Clock
Multiplier
Touch Load Buffer
Copy-Back Buffer
32-Bit Address Bus
32-/64-Bit Data Bus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
64-Bit (Two Instructions)
Branch
64-Bit
Processing
Unit
t
64-Bi
CTR
64-Bit (Two Instructions)
Instruction Unit
64-Bit
64-Bit
FPR File
FP Rename
Registers
+
32-Bit
64-Bit
DBAT
Array
16-Kbyte
D Cache
CR
LR
Floating-
Point Unit
+
/
*
FPSCR
I MMU
SRs
IBAT
Array
ITLB
16-Kbyte
Tags
I Cache
Core Interface
Freescale Semiconductor