Memory Map
Address
(offset)
0x11A17
SCC1 status register (SCCS1)
0x11A18–
Reserved
0x11A1F
0x11A20
SCC2 general mode register (low) (GSMR_L2)
0x11A24
SCC2 general mode register (high) (GSMR_H2)
0x11A28
SCC2 protocol-specific mode register (PSMR2)
0x11A2A
Reserved
0x11A2C
SCC2 transmit-on-demand register (TODR2)
0x11A2E
SCC2 data synchronization register (DSR2)
0x11A30
SCC2 event register (SCCE2)
0x11A34
SCC2 mask register (SCCM2)
0x11A36
Reserved
3-18
Table 3-1. Internal Memory Map (continued)
Register
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
R/W
Size
R/W
8 bits
—
8 bytes
SCC2
R/W
32 bits
R/W
32 bits
R/W
16 bits
—
16 bits
R/W
16 bits
R/W
16 bits
R/W
16 bits
R/W
16 bits
—
8 bits
Reset
Section/Page
0x00
21.20/21-21
(UART)
22.12/22-14
(HDLC)
23.15/23-16
(BISYNC)
24.13/24-12
(Transparent)
—
—
0x0000_0000
20.1.1/20-3
0x0000_0000
0x0000
20.1.2/20-9
21.16/21-12
(UART)
22.8/22-7
(HDLC)
23.11/23-10
(BISYNC)
24.9/24-8
(Transparent)
25.17/25-14
(Ethernet)
—
—
0x0000
20.1.4/20-10
0x7E7E
20.1.3/20-9
0x0000
21.19/21-19
(UART)
0x0000
22.11/22-12
(HDLC)
23.14/23-15
(BISYNC)
24.12/24-11
(Transparent)
25.20/25-20
(Ethernet)
—
—
Freescale Semiconductor