Figure
Number
21-5
21-6
21-7
21-8
21-9
21-10
21-11
21-12
22-1
HDLC Framing Structure...................................................................................................... 22-2
22-2
HDLC Address Recognition ................................................................................................. 22-4
22-3
22-4
22-5
22-6
22-7
22-8
22-9
CC HDLC Status Register (SCCS) ..................................................................................... 22-14
22-10
22-11
22-12
22-13
22-14
22-15
Delayed RTS Mode............................................................................................................. 22-21
22-16
23-1
Classes of BISYNC Frames.................................................................................................. 23-1
23-2
23-3
BISYNC SYNC (BSYNC) ................................................................................................... 23-7
23-4
BISYNC DLE (BDLE) ......................................................................................................... 23-8
23-5
23-6
SCC BISYNC RxBD .......................................................................................................... 23-12
23-7
23-8
23-9
24-1
Sending Transparent Frames between PowerQUICC IIs...................................................... 24-4
24-2
24-3
24-4
24-5
25-1
Ethernet Frame Structure ...................................................................................................... 25-1
25-2
Ethernet Block Diagram........................................................................................................ 25-2
25-3
Connecting the PowerQUICC II to Ethernet ........................................................................ 25-4
liv
Figures
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Title
Page
Number
Freescale Semiconductor