Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 58

Figure
Number
28-14 Transmitter Super Channel Example .................................................................................. 28-31
28-15 Receiver Super Channel with Slot Synchronization Example............................................ 28-32
28-16 Receiver Super Channel without Slot Synchronization Example....................................... 28-33
28-17 SI MCC Configuration Register (MCCF)........................................................................... 28-33
28-18 Interrupt Circular Table....................................................................................................... 28-36
28-19 MCC Event Register (MCCE)/Mask Register (MCCM).................................................... 28-37
28-20 Interrupt Circular Table Entry ............................................................................................. 28-38
28-21 MCC Receive Buffer Descriptor (RxBD)........................................................................... 28-43
28-22 MCC Transmit Buffer Descriptor (TxBD).......................................................................... 28-46
29-1 FCC Block Diagram.............................................................................................................. 29-3
29-2 General FCC Mode Register (GFMR).................................................................................. 29-4
29-3 FCC Data Synchronization Register (FDSR) ....................................................................... 29-8
29-4 FCC Transmit-on-Demand Register (FTODR)..................................................................... 29-9
29-5 FCC Memory Structure....................................................................................................... 29-10
29-6 Buffer Descriptor Format.................................................................................................... 29-10
29-7 Function Code Register (FCRx) ......................................................................................... 29-13
29-8 Output Delay from RTS Asserted ....................................................................................... 29-18
29-9 Output Delay from CTS Asserted ....................................................................................... 29-18
29-10 CTS Lost ............................................................................................................................. 29-19
29-11 Using CD to Control Reception .......................................................................................... 29-20
30-1 APC Scheduling Table Mechanism ...................................................................................... 30-9
30-2 VBR Pacing Using the GCRA (Leaky Bucket Algorithm) ................................................ 30-12
30-3 External CAM Data Input Fields ........................................................................................ 30-14
30-4 External CAM Output Fields .............................................................................................. 30-14
30-5 Address Compression Mechanism...................................................................................... 30-15
30-6 General VCOFFSET Formula for Contiguous VCLTs ....................................................... 30-16
30-7 VP Pointer Address Compression....................................................................................... 30-17
30-8 VC Pointer Address Compression ...................................................................................... 30-18
30-9 ATM Address Recognition Flowchart ................................................................................ 30-19
30-10 PowerQUICC II's ABR Basic Model ................................................................................. 30-20
30-11 ABR Transmit Flow ............................................................................................................ 30-22
30-12 ABR Transmit Flow (Continued)........................................................................................ 30-23
30-13 ABR Transmit Flow (Continued)........................................................................................ 30-24
30-14 ABR Receive Flow ............................................................................................................. 30-25
30-15 Rate Format for RM Cells................................................................................................... 30-26
30-16 Rate Formula for RM Cells................................................................................................. 30-26
30-17 Performance Monitoring Cell Structure (FMCs and BRCs)............................................... 30-29
30-18 FMC, BRC Insertion ........................................................................................................... 30-31
30-19 Format of User-Defined Cells............................................................................................. 30-32
30-20 External CAM Address in UDC Extended Address Mode................................................. 30-33
30-21 ATM-to-TDM Interworking................................................................................................ 30-34
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MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
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Freescale Semiconductor