Paragraph
Number
10.6
10.6.1
General System Clocks.............................................................................................. 10-5
10.7
PLL Pins ........................................................................................................................ 10-6
10.8
System Clock Control Register (SCCR)........................................................................ 10-8
10.9
System Clock Mode Register (SCMR).......................................................................... 10-9
10.10
Basic Power Structure.................................................................................................. 10-11
11.1
Features .......................................................................................................................... 11-3
11.2
Basic Architecture.......................................................................................................... 11-4
11.2.1
11.2.2
Page Hit Checking ..................................................................................................... 11-7
11.2.3
Error Checking and Correction (ECC) ...................................................................... 11-8
11.2.4
Parity Generation and Checking ................................................................................ 11-8
11.2.5
11.2.6
11.2.7
11.2.8
Atomic Bus Operation ............................................................................................... 11-9
11.2.9
Data Pipelining ......................................................................................................... 11-9
11.2.10
11.2.11
11.2.12
11.2.13
11.2.14
11.3
Register Descriptions ................................................................................................... 11-12
11.3.1
Base Registers (BRx) ............................................................................................... 11-13
11.3.2
Option Registers (ORx) ........................................................................................... 11-15
11.3.3
11.3.4
11.3.5
11.3.6
Memory Data Register (MDR) ................................................................................ 11-28
11.3.7
Memory Address Register (MAR) .......................................................................... 11-29
11.3.8
60x Bus-Assigned UPM Refresh Timer (PURT)..................................................... 11-30
11.3.9
Local Bus-Assigned UPM Refresh Timer (LURT) ................................................. 11-30
11.3.10
60x Bus-Assigned SDRAM Refresh Timer (PSRT)................................................ 11-31
11.3.11
Local Bus-Assigned SDRAM Refresh Timer (LSRT) ............................................ 11-31
11.3.12
Memory Refresh Timer Prescaler Register (MPTPR) ............................................. 11-32
11.3.13
11.3.14
xvi
Contents
Chapter 11
Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Title
Page
Number
Freescale Semiconductor