Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 142

G2 Core
Exception Vector Offset
Type
Program 00700
Floating-point 00800
unavailable
Decrementer 00900
Reserved 00A00–00BFF —
System call 00C00
Trace 00D00
Floating-point 00E00
assist
Reserved 00E10–00FFF —
Instruction 01000
translation
miss
Data load 01100
translation
miss
Data store 01200
translation
miss
Instruction 01300
address
breakpoint
System 01400
management
interrupt
Reserved 01500–02FFF —
2-24
Table 2-5. Exceptions and Conditions (continued)
(hex)
A program exception is caused by one of the following exception conditions, which
correspond to bit settings in SRR1 and arise during execution of an instruction:
• Illegal instruction—An illegal instruction program exception is generated when
execution of an instruction is attempted with an illegal opcode or illegal
combination of opcode and extended opcode fields (including PowerPC
instructions not implemented in the processor core), or when execution of an
optional instruction not provided in the processor core is attempted (these do not
include those optional instructions that are treated as no-ops).
• Privileged instruction—A privileged instruction type program exception is
generated when the execution of a privileged instruction is attempted and the
MSR register user privilege bit, MSR[PR], is set. In the processor core, this
exception is generated for mtspr or mfspr with an invalid SPR field if SPR[0] = 1
and MSR[PR] = 1. This may not be true for all processors that implement the
PowerPC architecture.
• Trap—A trap type program exception is generated when any of the conditions
specified in a trap instruction is met.
A floating-point unavailable exception is caused by an attempt to execute a
floating-point instruction (including floating-point load, store, and move instructions)
when the floating-point available bit is cleared (MSR[FP] = 0).
The decrementer exception occurs when the most significant bit of the decrementer
(DEC) register transitions from 0 to 1. Must also be enabled with the MSR[EE] bit.
A system call exception occurs when a System Call (sc) instruction is executed.
A trace exception is taken when MSR[SE] = 1 or when the currently completing
instruction is a branch and MSR[BE] = 1.
Not implemented.
An instruction translation miss exception is caused when the effective address for an
instruction fetch cannot be translated by the ITLB.
A data load translation miss exception is caused when the effective address for a
data load operation cannot be translated by the DTLB.
A data store translation miss exception is caused when the effective address for a
data store operation cannot be translated by the DTLB, or when a DTLB hit occurs,
and the changed bit in the PTE must be set due to a data store operation.
An instruction address breakpoint exception occurs when the address (bits 0–29) in
the IABR matches the next instruction to complete in the completion unit, and the
IABR enable bit (bit 30) is set.
A system management interrupt is caused when MSR[EE] = 1 and the SMI input
signal is asserted.
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Causing Conditions
Freescale Semiconductor