Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 708

SCC UART Mode
1
Offset Name
0x30 —
0x38 MAX_IDL
0x3A IDLC
0x3C BRKCR
0x3E PAREC
0x40 FRMEC
0x42 NOSEC
0x44 BRKEC
0x46 BRKLN
0x48 UADDR1
0x4A UADDR2
0x4C RTEMP
0x4E TOSEQ
0x50 CHARACTER1
0x52 CHARACTER2
0x54 CHARACTER3
0x56 CHARACTER4
0x58 CHARACTER5
0x5A CHARACTER6
0x5C CHARACTER7
0x5E CHARACTER8
21-4
Table 21-1. UART-Specific SCC Parameter RAM Memory Map
Width
DWord Reserved
Hword Maximum idle characters. When a character is received, the receiver begins
counting idle characters. If MAX_IDL idle characters are received before the next
data character, an idle timeout occurs and the buffer is closed, generating a
maskable interrupt request to the core to receive the data from the buffer. Thus,
MAX_IDL offers a way to demarcate frames. To disable the feature, clear
MAX_IDL. The bit length of an idle character is calculated as follows: 1 + data
length (5–9) + 1 (if parity is used) + number of stop bits (1–2). For 8 data bits, no
parity, and 1 stop bit, the character length is 10 bits.
Hword Temporary idle counter. Holds the current idle count for the idle timeout process.
IDLC is a down-counter and does not need to be initialized or accessed.
Hword Break count register (transmit). Determines the number of break characters the
transmitter sends. The transmitter sends a break character sequence when a
STOP TRANSMIT
1 start bit, each break character consists of 10 zero bits.
Hword User-initialized,16-bit (modulo–2
PAREC counts received parity errors.
Hword
FRMEC counts received characters with framing errors.
NOSEC counts received characters with noise errors.
Hword
BRKEC counts break conditions on the signal. A break condition can last for
Hword
hundreds of bit times, yet BRKEC is incremented only once during that period.
Hword Last received break length. Holds the length of the last received break character
sequence measured in character units. For example, if RXD x is low for 20 bit
times and the defined character length is 10 bits, BRKLN = 0x002, indicating that
the break sequence is at least 2 characters long. BRKLN is accurate to within
one character length.
Hword UART address character 1/2. In multidrop mode, the receiver provides automatic
address recognition for two addresses. In this case, program the lower order
Hword
bytes of UADDR1 and UADDR2 with the two preferred addresses.
Hword Temp storage
Hword Transmit out-of-sequence character. Inserts out-of-sequence characters, such
as XOFF and XON, into the transmit stream. The TOSEQ character is put in the
Tx FIFO without affecting a Tx buffer in progress. See
Control Characters into the Transmit Data
Hword Control character 1–8. These characters define the Rx control characters on
which interrupts can be generated.
Hword
Hword
Hword
Hword
Hword
Hword
Hword
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Description
command is issued. For 8 data bits, no parity, 1 stop bit, and
16
) counters incremented by the CP.
Section 21.11, "Inserting
Stream."
Freescale Semiconductor