Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 807

23. Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so the SMC1 can generate a
system interrupt. Initialize SIU interrupt pending register low (SIPNR_L) by writing
0xFFFF_FFFF to it.
24. Write 0x0000_0000 to GSMR_H2 to enable normal operation of all modes.
25. Write 0x1088_000C to the GSMR_L2 register to configure CTS (CLSN) and CD (RENA) to
automatically control transmission and reception (DIAG bits) and the Ethernet mode. TCI is set to
allow more setup time for the EEST to receive the PowerQUICC II transmit data. TPL and TPP
are set for Ethernet requirements. The DPLL is not used with Ethernet. Note that the ENT and ENR
are not enabled yet.
26. Write 0xD555 to the DSR.
27. Set the PSMR2 to 0x0A0A to configure 32-bit CRC, promiscuous mode, and begin searching for
the start frame delimiter 22 bits after RENA2 (CD2).
28. Write 0x1088_003C to GSMR_L2 to enable the SCC2 transmitter and receiver. This
additional write ensures that ENT and ENR are enabled last.
After 14 bytes and the 46 bytes of automatic pad (plus the 4 bytes of CRC) are sent, the TxBD is closed.
Additionally, the receive buffer is closed after a frame is received. Any data received after 1520 bytes or
a single frame causes a busy (out-of-buffers) condition because only one RxBD is prepared.
Freescale Semiconductor
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
SCC Ethernet Mode
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