Figure
Number
11-63
CS Signal Selection............................................................................................................. 11-75
11-64
BS Signal Selection............................................................................................................. 11-75
11-65
11-66
11-67
11-68
11-69
11-70
11-71
11-72
11-73
11-74
Exception Cycle .................................................................................................................. 11-89
11-75
11-76
11-77
11-78
11-79
11-80
11-81
11-82
11-83
11-84
11-85
11-86
12-1
12-2
12-3
12-4
Read Access with L2 Cache.................................................................................................. 12-8
13-1
Test Logic Block Diagram .................................................................................................... 13-2
13-2
13-3
Output Pin Cell (O.Pin)......................................................................................................... 13-4
13-4
13-5
13-6
14-1
14-2
14-3
14-4
14-5
14-6
14-7
Freescale Semiconductor
Figures
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Title
Page
Number
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