Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 171

Part II
Configuration and Reset
Intended Audience
Part II is intended for system designers and programmers who need to understand the operation of the
PowerQUICC II at start up. It assumes understanding of the PowerPC programming model described in
the previous chapters and a high level understanding of the PowerQUICC II.
Contents
Part II describes start-up behavior of the PowerQUICC II.
It contains the following chapters:
• Chapter 4, "System Interface Unit (SIU),"
functions which provide various monitors and timers, and the 60x bus configuration.
• Chapter 5, "Reset,"
Suggested Reading
Supporting documentation for the PowerQUICC II can be accessed through the world-wide web at
www.freescale.com. This documentation includes technical specifications, reference materials, and
detailed applications notes.
Conventions
This chapter uses the following notational conventions:
Bold
mnemonics
italics
0x0
0b0
rA, rB
rD
REG[FIELD]
Freescale Semiconductor
describes the behavior of the PowerQUICC II at reset and start-up.
Bold entries in figures and tables showing registers and parameter RAM should
be initialized by the user.
Instruction mnemonics are shown in lowercase bold.
Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
Prefix to denote hexadecimal number
Prefix to denote binary number
Instruction syntax used to identify a source GPR
Instruction syntax used to identify a destination GPR
Abbreviations or acronyms for registers or buffer descriptors are shown in
uppercase text. Specific bits, fields, or numerical ranges appear in brackets. For
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
describes the system configuration and protection
II-1