Figure
Number
32-7
CPS Tx Queue Descriptor (TxQD) ..................................................................................... 32-14
32-8
32-9
CPS TxBD........................................................................................................................... 32-16
32-10
CPS Packet Header Format................................................................................................. 32-17
32-11
SSSAR Tx Queue Descriptor.............................................................................................. 32-17
32-12
SSSAR TxBD ..................................................................................................................... 32-19
32-13
CID Mapping Process ......................................................................................................... 32-22
32-14
AAL2 Switching ................................................................................................................. 32-23
32-15
32-16
CPS Rx Queue Descriptor................................................................................................... 32-27
32-17
32-18
CPS Switch Rx Queue Descriptor ...................................................................................... 32-30
32-19
Switch Receive/Transmit Buffer Descriptor ....................................................................... 32-30
32-20
SSSAR Rx Queue Descriptor ............................................................................................. 32-32
32-21
SSSAR Receive Buffer Descriptor ..................................................................................... 32-33
32-22
UDC Header Table.............................................................................................................. 32-38
AAL2 Interrupt Queue Entry CID ≠ 0 ................................................................................ 32-39
32-23
32-24
33-1
Basic Concept of IMA .......................................................................................................... 33-5
33-2
Illustration of IMA Frames ................................................................................................... 33-6
33-3
IMA Microcode Overview.................................................................................................... 33-6
33-4
33-5
33-6
Transmit Queue Normal Operating State............................................................................ 33-14
33-7
Transmit Queue Behavior: Link Clock Rate Same as TRL ................................................ 33-14
33-8
33-9
Transmit Queue Behavior: Link Clock Rate Faster than TRL, Worst-Case
Event Sequence .............................................................................................................. 33-16
33-10
33-11
33-12
33-13
IMA Control (IMACNTL).................................................................................................. 33-29
33-14
33-15
33-16
33-17
33-18
33-19
33-20
Receive Group Order Table Entry....................................................................................... 33-40
33-21
33-22
Freescale Semiconductor
Figures
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Title
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Number
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