Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 168

Memory Map
Address
(offset)
0x11B03 Reserved
0x11B04 CPM mux FCC clock route register (CMXFCR)
0x11B08 CPM mux SCC clock route register (CMXSCR)
0x11B0C CPM mux SMC clock route register (CMXSMR)
0x11B0D Reserved
0x11B0E CPM mux UTOPIA address register (CMXUAR)
0x11B10– Reserved
0x11B1F
0x11B20 SI1 TDMA1 mode register (SI1AMR)
0x11B22 SI1 TDMB1 mode register (SI1BMR)
0x11B24 SI1 TDMC1 mode register (SI1CMR)
0x11B26 SI1 TDMD1 mode register (SI1DMR)
0x11B28 SI1 global mode register (SI1GMR)
0x11B29 Reserved
0x11B2A SI1 command register (SI1CMDR)
0x11B2B Reserved
0x11B2C SI1 status register (SI1STR)
0x11B2D Reserved
0x11B2E SI1 RAM shadow address register (SI1RSR)
0x11B30 MCC1 event register (MCCE1)
0x11B32 Reserved
0x11B34 MCC1 mask register (MCCM1)
0x11B36 Reserved
0x11B38 MCC1 configuration register (MCCF1)
0x11B39– Reserved
0x11B3F
3-22
Table 3-1. Internal Memory Map (continued)
Register
SI1 Registers
MCC1 Registers
6
6
6
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
R/W Size
— 8 bits
R/W 32 bits
R/W 32 bits
R/W 8 bits
— 8 bits
5
R/W 16 bits
— 16 bytes
R/W 16 bits
R/W 16 bits
R/W 16 bits
R/W 16 bits
R/W 8 bits
— 8 bits
R/W 8 bits
— 8 bits
R/W 8 bits
— 8 bits
R/W 16 bits
6
R/W 16 bits
— 16 bits
R/W 16 bits
— 16 bits
R/W 8 bits
— 7 bytes
Reset Section/Page
— —
0x0000_0000 16.4.4/16-13
0x0000_0000 16.4.5/16-16
0x00 16.4.6/16-19
— —
0x0000 16.4.1/16-7
— —
0x0000 15.5.2/15-17
0x0000
0x0000
0x0000
0x00 15.5.1/15-17
— —
0x00 15.5.4/15-24
— —
0x00 15.5.5/15-25
— —
0x0000 15.5.3/15-23
0x0000 28.8.1/28-37
—
0x0000 28.8.1/28-37
— —
0x00 28.6/28-33
— —
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