Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 157

Address
(offset)
0x11319 Reserved
0x1131C FCC1 transmit internal rate registers for PHY0
(FTIRR1_PHY0)
0x1131D FCC1 transmit internal rate registers for PHY1
(FTIRR1_PHY1)
0x1131E FCC1 transmit internal rate registers for PHY2
(FTIRR1_PHY2)
0x1131F FCC1 transmit internal rate registers for PHY3
(FTIRR1_PHY3)
0x11320 FCC2 general mode register (GFMR2)
0x11324 FCC2 protocol-specific mode register (FPSMR2)
0x11328 FCC2 transmit on-demand register (FTODR2)
0x1132A Reserved
0x1132C FCC2 data synchronization register (FDSR2)
0x1132E Reserved
0x11330 FCC2 event register (FCCE2)
0x11332 Reserved
0x11334 FCC2 mask register (FCCM2)
0x11336 Reserved
0x11338 FCC2 status register (FCCS2)
0x11339 Reserved
Freescale Semiconductor
Table 3-1. Internal Memory Map (continued)
Register
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
R/W Size
— 24 bits
R/W 8 bits
R/W 8 bits
R/W 8 bits
R/W 8 bits
FCC2
R/W 32 bits
R/W 32 bits
R/W 16 bits
— 16 bits
R/W 16 bits
— 16 bits
R/W 16 bits
— 16 bits
R/W 16 bits
— 16 bits
R 16 bits
— 24 bits
Memory Map
Reset Section/Page
— —
0x00 30.13.4/30-91
(ATM)
33.4.2.1.2/33-26
0x00
(IMA)
0x00
0x00
0x0000_0000 29.2/29-3
0x0000_0000 30.13.2/30-88
(ATM)
33.4.2.1.1/33-26
(IMA)
35.18.1/35-18
(Ethernet)
36.6/36-7
(HDLC)
0x0000 29.5/29-8
— —
0x7E7E 29.4/29-8
— —
0x0000_0000 30.13.3/30-90
(ATM)
35.18.2/35-20
(Ethernet)
36.9/36-14
(HDLC)
— —
0x0000_0000 30.13.3/30-90
(ATM)
35.18.2/35-20
(Ethernet)
36.9/36-14
(HDLC)
— —
0x00 36.10/36-16
(HDLC)
— —
3-11