Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 904

Fast Communications Controllers (FCCs)
Bits Name
8 CTSS CTS sampling
0 The CTS input is assumed to be asynchronous with the data. When it is internally synchronized
by the FCC, data is sent after a delay of no more than two serial clocks.
1 The CTS input is assumed to be synchronous with the data, giving faster operation. In this mode,
CTS must transition while the transmit clock is in the low state. As soon as CTS is low, data
transmission begins. This mode is useful when connecting PowerQUICC II in transparent mode
because it allows the RTS signal of one PowerQUICC II to be connected directly to the CTS
signal of another PowerQUICC II.
9--15 — Reserved, should be 0.
16–17 SYNL Sync length (transparent mode only). Determines the operation of an FCC receiver configured for
totally transparent operation only. See
00 The sync pattern in the FDSR is not used. An external sync signal is used instead (CD signal
01 Automatic sync (assumes always synchronized, ignores CD signal).
10 8-bit sync. The receiver synchronizes on an 8-bit sync pattern stored in the FDSR. Negation of
11 16-bit sync. The receiver synchronizes on a 16-bit sync pattern stored in the FDSR. Negation of
Note: If SYNL = 1x, CDP should be cleared (not in CD pulse mode).
18 RTSM RTS mode
0 Send idles between frames as defined by the protocol. RTS is negated between frames (default).
1 Send flags/syncs between frames according to the protocol. RTS is asserted whenever the FCC
is enabled.
19–20 RENC Receiver decoding method. The user should set RENC = TENC in most applications.
00 NRZ
01 NRZI (one bit mode HDLC or transparent only)
1x Reserved
21 REVD Reverse data (valid for a totally transparent channel only)
0 Normal operation
1 The totally transparent channels on this FCC (either the receiver, transmitter, or both, as defined
by TTX and TRX) reverse bit order, transmitting the MSB of each octet first.
22–23 TENC Transmitter encoding method. The user should set TENC = RENC in most applications.
00 NRZ
01 NRZI (one bit mode HDLC or transparent only)
1x Reserved
24-25 TCRC Transparent CRC (totally transparent channel only). Selects the type of frame checking provided on
the transparent channels of the FCC (either the receiver, transmitter, or both, as defined by TTX and
TRX). This configuration selects a frame check type; the decision to send the frame check is made
in the TxBD. Thus, it is not required to send a frame check in transparent mode. If a frame check is
not used, the user can ignore any frame check errors generated on the receiver.
00 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1)
01 Reserved
10 32-bit CCITT CRC (Ethernet and HDLC) (X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +
11 Reserved
29-6
Table 29-2. GFMR Register Field Descriptions (continued)
asserted: high to low transition).
CD causes CD lost error.
CD causes CD lost error.
X8 + X7 + X5 + X4 + X2 + X1 +1)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Description
Section 37.3.1, "In-Line Synchronization Pattern."
Freescale Semiconductor