Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 17

Paragraph
Number
9.13.1.6.2
9.13.1.6.3
9.13.1.6.4
9.13.1.6.5
9.13.1.6.6
9.13.1.6.7
9.13.2 DMA Segment Descriptors........................................................................................ 9-95
9.13.2.1 Descriptor in Big Endian Mode............................................................................. 9-96
9.13.2.2 Descriptor in Little Endian Mode .......................................................................... 9-97
9.14 Error Handling ............................................................................................................... 9-97
9.14.1 Interrupt and Error Signals ........................................................................................ 9-97
9.14.1.1 PCI Bus Error Signals............................................................................................ 9-97
9.14.1.1.1
9.14.1.1.2
9.14.1.1.3
9.14.1.2 Illegal Register Access Error ................................................................................. 9-98
9.14.1.3 PCI Interface.......................................................................................................... 9-98
9.14.1.3.1
9.14.1.3.2
9.14.1.3.3
9.14.1.3.4
9.14.1.3.5
9.14.1.4 Embedded Utilities .............................................................................................. 9-100
9.14.1.4.1
9.14.1.4.2
9.14.1.4.3
10.1 Clock Unit...................................................................................................................... 10-1
10.2 Clock Configuration ...................................................................................................... 10-1
10.3 External Clock Inputs .................................................................................................... 10-1
10.4 Main PLL ....................................................................................................................... 10-2
10.4.1 PLL Block Diagram................................................................................................... 10-2
10.4.2 Skew Elimination....................................................................................................... 10-3
10.4.3 PCI Bridge Clocking.................................................................................................. 10-3
10.4.3.1 PCI Bridge as an Agent Operating from the PCI System Clock ........................... 10-3
10.4.3.2 PCI Bridge as a Host and Generating the PCI System Clock................................ 10-4
10.4.3.2.1
10.5 Clock Dividers ............................................................................................................... 10-5
Freescale Semiconductor
Contents
DMA Status Register [0-3] (DMASRx) .......................................................... 9-90
DMA Current Descriptor Address Register [0-3] (DMACDARx) .................. 9-91
DMA Source Address Register [0-3] (DMASARx) ........................................ 9-92
DMA Destination Address Register [0-3] (DMADARx) ................................ 9-92
DMA Byte Count Register [0-3] (DMABCRx) ............................................... 9-93
DMA Next Descriptor Address Register [0-3] (DMANDARx) ...................... 9-94
System Error (SERR) ........................................................................................ 9-98
Parity Error (PERR)........................................................................................... 9-98
Error Reporting.................................................................................................. 9-98
Address Parity Error .......................................................................................... 9-99
Data Parity Error................................................................................................ 9-99
Master-Abort Transaction Termination ............................................................. 9-99
Target-Abort Error ........................................................................................... 9-100
NMI ................................................................................................................. 9-100
Outbound Free Queue Overflow ..................................................................... 9-100
Inbound Post Queue Overflow ........................................................................ 9-100
Inbound DoorBell Machine Check.................................................................. 9-100
Clocks and Power Control
CPM CLOCK and PCI Frequency Equations ................................................... 10-5
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Title
Chapter 10
Page
Number
xv