Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 892

Multi-Channel Controllers (MCCs)
Bits Name
0 E Empty
0 The data buffer associated with this BD has been filled with received data, or data reception has
been aborted due to an error condition. The user is free to examine or write to any fields of this
RxBD. The CP does not use this BD again while the empty bit remains zero.
1 The data buffer associated with this BD is empty, or reception is in progress. This RxBD and its
associated receive buffer are in use by the CP. When E = 1, the user should not write any fields
of this RxBD.
1 — Reserved, should be cleared.
2 W Wrap (final BD in table)
0 This is not the last BD in the RxBD table.
1 This is the last BD in the RxBD table. After this buffer has been used, the CP receives incoming
data into the first BD in the table (the BD pointed to by RBASE). The number of RxBDs in this
table is programmable and is determined by the wrap bit.
3 I Interrupt
0 The RXB bit is not set after this buffer has been used, but RXF operation remains unaffected.
1 The RXB or RXF bit in the HDLC interrupt circular table entry is set when this buffer has been
used by the HDLC controller. These two bits may cause interrupts (if enabled).
4 L Last in frame (only for HDLC mode of operation). The HDLC controller sets L = 1, when this buffer
is the last in a frame. This implies the reception either of a closing flag or of an error, in which case
one or more of the CD, OV, AB, and LG bits are set. The HDLC controller writes the number of frame
octets to the data length field.
0 This buffer is not the last in a frame.
1 This buffer is the last in a frame.
5 F First in frame. The HDLC controller sets F = 1 for the first buffer in a frame. In transparent mode, F
indicates that there was a synchronization before receiving data in this BD.
0 This is not the first buffer in a frame.
1 This is the first buffer in a frame.
6 CM Continuous mode
0 Normal operation (The empty bit (bit 0) is cleared by the CP after this BD is closed).
1 The empty bit (bit 0) is not cleared by the CP after this BD is closed, allowing the associated data
buffer to be overwritten automatically when the CP next accesses this BD. However, if an error
occurs during reception, the empty bit is cleared regardless of the CM bit setting.
7 — Reserved, should be cleared.
8 UB User bit. UB is a user-defined bit that the CPM never sets nor clears. The user determines how this
bit is used.
9 — Reserved, should be cleared.
10 LG Rx frame length violation (HDLC mode only). Indicates that a frame length greater than the
maximum value was received in this channel. Only the maximum-allowed number of bytes, MFLR
rounded to the nearest higher word alignment, are written to the data buffer. This event is recognized
as soon as the MFLR value is exceeded when data is word-aligned. When data is not word-aligned,
this interrupt occurs when the SDMA writes 64 bits to memory. The worst-case latency from MFLR
violation until detected is 7 bytes timing for this channel. When MFLR violation is detected, the
receiver is still receiving even though the data is discarded. The buffer is closed upon detecting a
flag, and this is considered to be the closing flag for this buffer. At this point, LG is set (1) and an
interrupt may be generated. The length field for this buffer is everything between the opening flag
and this last identifying flag.
28-44
Table 28-22. RxBD Field Descriptions
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Description
Freescale Semiconductor