Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 12

Paragraph
Number
7.2.4.4.2
7.2.4.5 Caching-Inhibited (CI)-Output ............................................................................. 7-8
7.2.4.6 Write-Through (WT)-Output ................................................................................ 7-9
7.2.5 Address Transfer Termination Signals......................................................................... 7-9
7.2.5.1 Address Acknowledge (AACK) .............................................................................. 7-9
7.2.5.1.1
7.2.5.1.2
7.2.5.2 Address Retry (ARTRY)........................................................................................ 7-10
7.2.5.2.1
7.2.5.2.2
7.2.6 Data Bus Arbitration Signals ..................................................................................... 7-11
7.2.6.1 Data Bus Grant (DBG) .......................................................................................... 7-11
7.2.6.1.1
7.2.6.1.2
7.2.6.2 Data Bus Busy (DBB) ........................................................................................... 7-12
7.2.6.2.1
7.2.6.2.2
7.2.7 Data Transfer Signals................................................................................................. 7-12
7.2.7.1 Data Bus (D[0-63]) ............................................................................................... 7-12
7.2.7.1.1
7.2.7.1.2
7.2.7.2 Data Bus Parity (DP[0-7])..................................................................................... 7-13
7.2.7.2.1
7.2.7.2.2
7.2.8 Data Transfer Termination Signals ............................................................................ 7-14
7.2.8.1 Transfer Acknowledge (TA) .................................................................................. 7-14
7.2.8.1.1
7.2.8.1.2
7.2.8.2 Transfer Error Acknowledge (TEA)...................................................................... 7-16
7.2.8.2.1
7.2.8.2.2
7.2.8.3 Partial Data Valid Indication (PSDVAL) ............................................................... 7-16
7.2.8.3.1
7.2.8.3.2
8.1 Terminology..................................................................................................................... 8-1
8.2 Bus Configuration............................................................................................................ 8-2
8.2.1 Single-PowerQUICC II Bus Mode .............................................................................. 8-2
x
Contents
Global (GBL)-Input .......................................................................................... 7-8
Address Acknowledge (AACK)-Output........................................................... 7-9
Address Acknowledge (AACK)-Input ............................................................. 7-9
Address Retry (ARTRY)-Output .................................................................... 7-10
Address Retry (ARTRY)-Input ....................................................................... 7-10
Data Bus Grant (DBG)-Input.......................................................................... 7-11
Data Bus Grant (DBG)-Output ....................................................................... 7-11
Data Bus Busy (DBB)-Output ........................................................................ 7-12
Data Bus Busy (DBB)-Input ........................................................................... 7-12
Data Bus (D[0-63])-Output ............................................................................ 7-13
Data Bus (D[0-63])-Input............................................................................... 7-13
Data Bus Parity (DP[0-7])-Output ................................................................. 7-13
Data Bus Parity (DP[0-7])-Input .................................................................... 7-14
Transfer Acknowledge (TA)-Input ................................................................. 7-14
Transfer Acknowledge (TA)-Output............................................................... 7-15
Transfer Error Acknowledge (TEA)-Input ..................................................... 7-16
Transfer Error Acknowledge (TEA)-Output................................................... 7-16
Partial Data Valid (PSDVAL)-Input................................................................ 7-16
Partial Data Valid (PSDVAL)-Output ............................................................. 7-17
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Title
Chapter 8
The 60x Bus
Page
Number
Freescale Semiconductor