Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 500

Memory Controller
After timings are created, programming the UPM continues with translating these timings into tables
representing the RAM array contents for each possible cycle. When a table is completed, the global
parameters of the UPM must be defined for handling the disable timer (precharge) and the refresh timer
relative to Figure 11-67.
Machine select UPMA
Port size 64-bit
No write protect (R/W)
Refresh timer value (1024 refresh cycles)
Refresh timer enable
Address multiplex size
Disable timer period
Select between GPL4 and UPMWAIT = GPL4 data sample at clock rising edge
Burst inhibit device
The OR and BR of the specific bank must be initialized according to the address mapping of the DRAM
device used. The MS field should indicate the specific UPM selected to handle the cycle. The RAM array
of the UPM can than be written through use of the MxMR[OP] = 11.
addressed by the UPM, according to the different services required by the DRAM.
CLKIN
A
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
11-82
Table 11-42 shows settings of different fields.
Table 11-42. UPMs Attributes Example
Explanation
Row Column 1
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Field
BR x [MS]
BR x [PS]
BR x [WP]
PURT[PURT]
M x MR[RFEN]
M x MR[AM x ]
M x MR[DS x ]
M x MR[GPL_x4DIS]
OR x [BI]
Figure 11-56 shows the first locations
Freescale Semiconductor
Value
0b100
0b00
0b0
0x0C
0b1
0b010
0b01
0b0
0b0