Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 440

Memory Controller
Bits Name
14–16 RFRC
17–19 PRETOACT Precharge to activate interval. Defines the earliest timing for
20–22 ACTTORW Activate to read/write interval. Defines the earliest timing for
23 BL
24–25 LDOTOPRE Last data out to precharge. Defines the earliest timing for
26–27 WRC
11-22
Table 11-8. PSDMR Field Descriptions (continued)
SDRAM Device–Specific Parameters:
Refresh recovery. Defines the earliest timing for an activate command after a
command. Sets the refresh recovery interval in clock cycles. See
Recovery Interval (RFRC)," for how to set this field.
000 Reserved
001 3 clocks
010 4 clocks
011 5 clocks
100 6 clocks
101 7 clocks
110 8 clocks
111 16 clocks
after a precharge command. See
001 1 clock-cycle wait states
010 2 clock-cycle wait states
...
111 7 clock-cycle wait states
000 8 clock-cycle wait states
command. See Section 11.4.6.2, "Activate to Read/Write
ACTIVATE
001 1 clock cycle
010 2 clock cycles
...
111 7 clock cycles
000 8 clock cycles
Burst length
0 SDRAM burst length is 4. Use this value if the device port size is 64 or 16
1 SDRAM burst length is 8. Use this value if the device port size is 32 or 8
data was read from the SDRAM. See
00 0 clock cycles
01 -1 clock cycle
10 -2 clock cycles
11 Reserved
Note: A value of 0b00 (0 clock cycles) gives the longest time while a value of 0b10 (-2 clock
cycles) gives the least.
Write recovery time. Defines the earliest timing for
written to the SDRAM. See
01 1 clock cycles
10 2 clock cycles
11 3 clock cycles
00 4 clock cycles
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Description
Section 11.4.6.1, "Precharge-to-Activate
Section 11.4.6.4, "Last Data Out to
PRECHARGE
Section 11.4.6.5, "Last Data In to Precharge—Write
REFRESH
Section 11.4.6.6, "Refresh
or command
ACTIVATE REFRESH
Interval."
/ command after an
READ WRITE
Interval."
command after the last
PRECHARGE
Precharge."
command after the last data was
Recovery."
Freescale Semiconductor