Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 289

Program Transfer
Size
Word
Double-Word
1
OP n : These lanes are read or written during that bus transaction. OP0 is the most-significant byte of a word operand
and OP7 is the least-significant byte.
2
—: These lanes are ignored during reads and driven with undefined data during writes.
The PowerQUICC II supports misaligned memory operations, although they may degrade performance
substantially. A misaligned memory address is one that is not aligned to the size of the data being
transferred (such as, a word read from an odd byte address). The PowerQUICC II's processor bus interface
supports misaligned transfers within a word (32-bit aligned) boundary, as shown in
the 4-byte transfer in Table 8-7
does not cross a word boundary, the PowerQUICC II can transfer the data to the misaligned address within
a single bus transfer (for example, a half-word read from an odd byte-aligned address). It takes two bus
transfers to access data that crosses a word boundary.
Due to the performance degradation, misaligned memory operations should be avoided. In addition to the
double-word straddle boundary condition, the processor's address translation logic can generate
substantial exception overhead when the load/store multiple and load/store string instructions access
misaligned data. It is strongly recommended that software attempt to align code and data where possible.
Program Size of
Word (4 bytes)
Aligned
Misaligned—1st access
2nd access
Misaligned—1st access
2nd access
Misaligned—1st access
2nd access
Aligned
Misaligned—1st access
2nd access
Freescale Semiconductor
Table 8-6. Aligned Data Transfers (continued)
TSIZ[0–3] A[29–31]
0 1 0 0 0 0 0
0 1 0 0 1 0 0
0 0 0 0 0 0 0
is only one example of misalignment. As long as the attempted transfer
Table 8-7. Unaligned Data Transfer Example (4-Byte Example)
TSIZ[1–3] A[29–31]
1 0 0 0 0 0
0 1 1 0 0 1
0 0 1 1 0 0
0 1 0 0 1 0
0 1 0 1 0 0
0 0 1 0 1 1
0 1 1 1 0 0
1 0 0 1 0 0
0 1 1 1 0 1
0 0 1 0 0 0
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Data Bus Byte Lanes
D0... ...D31
B0 B1 B2 B3
OP0 OP1 OP2 OP3
— — — —
OP0 OP1 OP2 OP3
Data Bus Byte Lanes
D0... ...D31
B0 B1 B2
1
A A A
— A A
— — —
— — A
— — —
— — —
— — —
— — —
— — —
A — —
D32... ...D63
B4 B5 B6
— — —
OP4 OP5 OP6
OP4 OP5 OP6
Table 8-7. Note that
D32... ...D63
B3 B4 B5 B6
2
A — — —
A — — —
— A — —
A — — —
— A A —
A — — —
— A A A
— A A A
— — A A
— — — —
The 60x Bus
B7
—
OP7
OP7
B7
—
—
—
—
—
—
—
A
A
—
8-15