Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 628

CPM Multiplexing
Bits Name
17 SC3 SCC3 connection
0 SCC3 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O
control register.
1 SCC3 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.
18–20 RS3CS Receive SCC3 clock source (NMSI mode). Ignored if SCC3 is connected to the TSA (SC3 = 1).
000 SCC3 receive clock is BRG1.
001 SCC3 receive clock is BRG2.
010 SCC3 receive clock is BRG3.
011 SCC3 receive clock is BRG4.
100 SCC3 receive clock is CLK5.
101 SCC3 receive clock is CLK6.
110 SCC3 receive clock is CLK7.
111 SCC3 receive clock is CLK8.
21–23 TS3CS Transmit SCC3 clock source (NMSI mode). Ignored if SCC3 is connected to the TSA (SC3 = 1).
000 SCC3 transmit clock is BRG1.
001 SCC3 transmit clock is BRG2.
010 SCC3 transmit clock is BRG3.
011 SCC3 transmit clock is BRG4.
100 SCC3 transmit clock is CLK5.
101 SCC3 transmit clock is CLK6.
110 SCC3 transmit clock is CLK7.
111 SCC3 transmit clock is CLK8.
24 GR4 Grant support of SCC4
0 SCC4 transmitter does not support the grant mechanism. The grant is always asserted internally.
1 SCC4 transmitter supports the grant mechanism as determined by the GMx bit of a serial device
channel.
25 SC4 SCC4 connection
0 SCC4 is not connected to the TSA and is either connected directly to the NMSIx pins or is not
used. The choice of general-purpose I/O port pins versus SCCn pins is made in the parallel I/O
control register.
1 SCC4 is connected to TSA of the SIs. The NMSIx pins are available for other purposes.
16-18
Table 16-6. CMXSCR Field Descriptions (continued)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Description
Freescale Semiconductor