Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 3

Part II—Configuration and Reset
System Interface Unit (SIU)
Part III—The Hardware Interface
Secondary (L2) Cache Support
IEEE 1149.1 Test Access Port
Part IV—Communications Processor Module
Communications Processor Module Overview
Serial Interface with Time-Slot Assigner
Baud-Rate Generators (BRGs)
SDMA Channels and IDMA Emulation
Serial Communications Controllers (SCCs)
Serial Management Controllers (SMCs)
Multi-Channel Controllers (MCCs)
Fast Communications Controllers (FCCs)
ATM Controller and AAL0, AAL1, and AAL5
ATM AAL1 Circuit Emulation Service
Inverse Multiplexing for ATM (IMA)
ATM Transmission Convergence Layer
Part I—Overview
Overview
G2 Core
Memory Map
Reset
External Signals
60x Signals
The 60x Bus
PCI Bridge
Clocks and Power Control
Memory Controller
CPM Multiplexing
Timers
SCC UART Mode
SCC HDLC Mode
SCC BISYNC Mode
SCC Transparent Mode
SCC Ethernet Mode
SCC AppleTalk Mode
ATM AAL2
I
1
2
3
II
4
5
III
6
7
8
9
10
11
12
13
IV
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34