Figure
Number
11-22
CL = 2 (2 Clock Cycles) ..................................................................................................... 11-40
11-23
11-24
WRC = 2 (2 Clock Cycles) ................................................................................................. 11-41
11-25
RFRC = 4 (6 Clock Cycles) ................................................................................................ 11-42
11-26
EAMUX = 1........................................................................................................................ 11-42
11-27
BUFCMD = 1...................................................................................................................... 11-43
11-28
11-29
11-30
11-31
11-32
11-33
11-34
11-35
11-36
11-37
SDRAM Mode-Set Command Timing ............................................................................... 11-47
11-38
Mode Data Bit Settings ....................................................................................................... 11-47
11-39
11-40
11-41
11-42
11-43
11-44
GPCM Memory Device Basic Timing (ACS ≠ 00, CSNT = 1, TRLX = 0)....................... 11-56
11-45
11-46
11-47
11-48
11-49
11-50
11-51
11-52
11-53
11-54
11-55
11-56
RAM Array Indexing .......................................................................................................... 11-65
11-57
11-58
11-59
Memory Controller UPM Clock Scheme for Non-Integer (2.5:1/3.5:1) Clock Ratios....... 11-68
11-60
11-61
11-62
The RAM Word................................................................................................................... 11-70
l
Figures
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Title
Page
Number
Freescale Semiconductor