Freescale Semiconductor MPC8260 PowerQUICC II Family Reference Manual page 442

Memory Controller
Bits Name
2–4 OP
5–7 SDAM
8–10 BSMA
11–13 SDA10
11-24
Table 11-9. LSDMR Field Descriptions (continued)
SDRAM operation. Selects the operation that occurs when the SDRAM device is accessed.
000 Normal operation
001 CBR refresh, used in SDRAM initialization.
010 Self refresh (for debug purpose).
011 Mode Register write, used in SDRAM initialization.
100 Precharge bank (for debug purpose).
101 Precharge all banks, used in SDRAM initialization.
110 Activate bank (for debug purpose).
111 Read/write (for debug purpose).
Address multiplex size. Determines how the address of the current memory cycle is output on
the address pins. See Section 11.4.5.2, "SDRAM Address Multiplexing (SDAM and
Bank select multiplexed address line. Selects which PowerQUICC II address pins serve as
bank-select address for the local bus SDRAM. See
Multiplexing (SDAM and BSMA)."
000 L_A14 (OR x [BPD] must be 00)
001 L_A–L_A15 (OR x [BPD] must be 00 or 01)
010 L_A14–L_A16
011 L_A15–L_A17
100 L_A16–L_A18
101 L_A17–L_A19
110 L_A18–L_A20
111 L_A19–L_A21
"A10" control. When SDRAM is selected, with LSDMR[PBI], determines which address line is
output to SDA10 during an
Section 11.4.12.1, "SDRAM Configuration Example (Page-Based
For PBI=0: For PBI=1:
000 A12 000 A10
001 A11 001 A9
010 A10 010 A8
011 A9 011 A7
100 A8 100 A6
101 A7 101 A5
110 A6 110 A4
111 A5 111 A3
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Description
Section 11.4.5.2, "SDRAM Address
command, to control the memory access. See
ACTIVATE
BSMA)."
Interleaving)."
Freescale Semiconductor